CSE3201
Digital Logic Design
Lab 4 many of you (all but one) did not finish this lab in time. You can submit it with lab 5.
It is much easier if you make your code modular, first write a module for full_adder, then you can use it to implement the regular adder. here is a tutorial, in the first 2 pages, it shows you how to write a module "mynand" and then use it to implement "somefunction"
many of you found some difficulties writing the Verilog code for the ful adder problem. I am posting here some modules for a 4-bit adder. These modules were successfully compiled and simulated. and 4, full adder, half adder, 4-bit adder,
The testbench for the above adder, and the verilog simulator
The deadline to submit the prject proposal is Friday Nov. 9th