CSE3201

Digital Logic Design

General Information

 

Course Information

 

Grading Policy

 

Lecture Schedule

 

Homework and Exercise

 

Lab

 

Exam information

After every chapter, some exercise problems will be posted here. These problems are neither collected or marked. They will help you in the quizzes and test. A solution will be distributed in the class after the due date of the assignment.

HW1 Due Sept. 26th 2007

HW2 due Sept. 28th 2007

here are sombrief tutorials/notes to help with Verilog style, tutorial, and design tips

Veriwell simulator

 

HW3 Due Nov. 7th, 2007

HW4 Due Nov. 21, 2007

HW5 Due Nov. 26, 2007