CSE3201
Digital Logic Design
Some parts of the slides posted here are just a skeleton that will be filled-in in the lecture. The filled slides will not be posted. If you missed a lecture, please be sure to get the slides from someone who attended it.
Week of Lectures Extra 9/3 Chapter 1 Introduction 1up and 2up 9/10 CMOS 1up 2up and Chapter 2 9/17 Chapter 3 part 1 Lab 1 is ready 9/24 Chapter 3 part 2 Lab 2 is ready 10/1 Chapter 4 Lab 3 is ready 10/8 Continue with Chapter 4 Quiz 1 Friday 12, No lab 10/15 Cont. Chapter 4, PLD, and hazards Lab 4 is ready
look in HW and Excercise for some verilog tips/help
10/22 Chapter 5 Synchronous Sequential Logic MIDTERM lab 5 is ready 10/29 Continue with Sequential Logic 11/5 Sequential Logic Lab 8 is ready 11/12 Chapter 6 Registers and Counters Continue with Lab 8 11/19 Memory and RTL Project 11/26 Chapter 8 Project 12/3