CSE3201

Digital Logic Design

General Information

 

Course Information

Grading Policy

Lecture Schedule

Homework and Exercise

Lab

Project

Exam information

Week of 11/17Lectures Announcements
9/5 Introduction and numbr systems  
9/12 CMOS circuits and logic gates  
9/19 Boolean Algebra  
9/26 Minimization HW1 is out Check the lab page for Verilog slides
10/3 cont. Quiz 1
10/10 Reading week Lab 4 is ready -- Also, look at the project page
10/17 Con  
10/24 Combinational Circuits Midterm, lab 6 is ready Submit your project idea
10/31 Sequential Circuits Quiz 2 posponed to the week of 11/7
11/7 Cont. sequential circuits LCD user manual
11/14 Registers and counters  
11/21 RTL and ASM slides corrected 11/24
11/28 Timing analysis (no slides) Quiz 3 Friday
12/5   project Demo