Write a small Verilog module itmult that has two multibit
outputs of size SIZE HM and LM
which are the high and low bits of the result, two multibit inputs of size
SIZE A and B which are the
operands, one single bit output fin that signals the end of
the iterative computation, and three inputs:
start that tells the circuit when to use the input operands
to calculate
the product, so when start is zero it keeps copying the
inputs A and B and when it switches to one it
starts the multiplication which will take SIZE
cycles. The operation is pretty much like the notes from chapter 3
(pg. 8). You will need to instantiate, possibly among other things, a
register rregister to accumulate the result which has to be
big enough to hold both the low and the high bits, a
counter cntr to count the number of iterations, an
adder yAdder and a two-to-one multiplexor yMux.
To start download file LabTestII.v and with the help of this diagram
implement module itmult. Notice that there is no cntr in the
diagram but it is needed in the module itmult.
To test your circuit create a separate module named LabN
where you
instantiate module itmult and include an initial that toggles the
clk. Please note the use of the resettable modules (ie, they have an extra
input reset)