;
;***************************************************************************
; Customization Data for D-Bug12 v4.x.x
;
; This data MUST reside at address $eec0
;***************************************************************************
;
FDIV8:	equ	$40
;
	org	$eec0
;
OscClk:	equ	8000000
Eclock:	equ	24000000		; PLL E-clock frequency.
RefClock:	equ	8000000		; reference clock frequency used by PLL.
;
UserCCR:	dc.b	$90		; initial CCR register value for EVB mode.
UserB:	dc.b	$00		; initial B accumulator value for EVB or POD mode.
UserA:	dc.b	$00		; initial A accumulator value for EVB or POD mode.
UserX:	dc.w	$0000		; initial X index register value for EVB or POD mode.
UserY	dc.w	$0000		; initial Y index register value for EVB or POD mode.
UserPC:	dc.w	$0000		; initial PC value for EVB or POD mode.
UserSP:	dc.w	$3c00		; initial user PC value for EVB mode.
BusClk:	dc.l	Eclock		; system bus (E-clock) frequency.
REFDVVal:	dc.b	(OscClk/RefClock)-1
SYNRVal:	dc.b	(Eclock/RefClock)-1
	if	OscClk>12800000
FCLKDIVVal:	dc.b	(OscClk/200000/8)+FDIV8	; value for FCLKDIV & ECLKDIV register.
	else
FCLKDIVVal:	dc.b	(OscClk/200000)		; value for FCLKDIV & ECLKDIV register.
	endif
IOBase:	dc.w	$0000		; I/O register base address.
SCIBRegVal:	dc.w	Eclock/16/9600		; initial baud register value (9600 baud)
EEBase:	dc.w	$0400		; on-chip EEPROM base address available to D-Bug12.
EESize:	dc.w	3072		; on-chip EEPROM size available to D-Bug12.
EEDelay:	dc.w	$ef02		; adress of 1 mS * D delay routine in supplied startup code.
DlyCnt:	dc.w	Eclock/4000
;
