CSE4210.3.0M Architecture
& Hardware for DSP
(Winter 2010)
Instructor: Prof. Hui Jiang
Time: MW 13:0014:30 (@SC303)
Office Hours:
MW 15:0016:00 (@CSEB3014)
Announcements: (refresh your browser)
á
Apr 14: Unofficial grades
are available from ePost.
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Apr 5:
Solutions to some A2 questions are posted here.
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Mar 29: Lecture notes for Part 10 posted below.
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Mar 23: A2 has been posted below.
á Mar 15: Lecture notes for Part 9 posted below. The class on March 17 (Wed) has been canceled since the instructor is going to a conference. The course evaluation has been scheduled for this class on March 24^{th} (Wed).
á Mar 8: Lecture notes for Part 8 posted below. Lab4 is also posted below.
á Mar 1: Lecture notes for Part 7 posted below, along with some memory design examples, ram.v, ram_dual.v, rom.v. Other designs related to the DCTQ processors, dctq.v, dualram.v, romc.v and romq.v.
á Feb 22: Lab 3 writeup is posted below. The due date for lab2 report is extended to March 3. TA will collect the reports before the lab session on March 3 and no further extension will be allowed.
á Feb 8: Lecture notes for Part 6 are also posted below.
á Feb 3: Assignment one is posted below. Lecture notes for Part 5 are also posted below.
á Feb 1: Midterm exam is scheduled in class on Feb 24^{th} (Wednesday).
á Jan 27: Some arithmetic circuit design examples, serial_adder.v, parallel_adder.v and mul11s_8s.v. Lecture notes (Part 4) are posted below.
á Jan 20: Fixedpoint examples are posted1 here for lab1. Lecture notes (Part 3) are posted below.
á Jan 13: Lab1 writeup is updated. Please download it again and notice all the updates in red.
á Jan 11: Lecture notes (Part 2) are posted below. Lab1 starts tomorrow (Jan 12). The lab is scheduled in the digital logic lab (CSE1004A). CSE1004A is open during the regular PRISM lab hours so that you can go anytime besides the scheduled lab sessions. Also, all students in our class have been granted the permission to access the thirdfloor ISPM lab (CSE3057) for working on extra hours.
á Jan 6: A C program example used in class: convolution.c. Lab1 is posted below. The first lab session will officially start from next Tuesday.
á Jan 4: Lecture notes (Part 1) are posted below. Two articles regarding 3D audio are posted as well and please start to read them to prepare for Lab1.
á Dec 27: Our first class starts on Jan 4.
This course presents basic VLSI concepts and design techniques for DSP systems, including iteration bound, pipeline and parallel processing, retiming, unfolding, folding and so on. Some case studies are presented for DSP arithmetic circuit design using both DSP processors and FPGA.
The required textbook:
[1] K. K. Parhi, VLSI
Digital Signal Processing Systems, John
Wiley & Sons, Inc., 1999, ISBN:
0471241865.
Other
reference materials:
[1] S. Ramachandran,
Digital VLSI Systems Design,
Springer, 2007, ISBN 9781402058288.
[2] A. V. Oppenheim, R. W. Schafer and J. R. Buck, Discretetime Signal Processing, Prentice Hall, ISBN 0137549202.
[3] F. Vahid and R. Lysecky, Verilog for Digital Design, Wiley, ISBN13 9780470052624.
Downloads:
Assignments 










Lecture notes 


Lab Schedule (subject to change)
We have four labs in this course. The lab will continue through the reading week.
Projectrelated readings: 3D Audio (I), 3D Audio (II), HRTFCIPIC database
Downloads: horse.wav, highheel.wav.
Quartus II tutorial is here for Lab24. Timing analysis in Quartus II.
Reading for lab4: DE2 Tutorial, Karaoke demo and audio CODEC datasheet.


Lab Sessions 
Report Due 
4 weeks 
Jan 12, Jan 19 Jan 26, Feb 2 
Feb 2 

3 weeks 
Feb 9, Feb 16, Feb 23 
Mar 2 

2 weeks 
Mar 2, Mar 9 
Mar 9 

3 weeks 
Mar 16, Mar 23, Mar 30 
Mar 30 
Evaluation:
(1)
(10%) Assignments
(2)
(30%) Lab Projects
(3) (25%) Midterm
(4)
(35%)
Final
Week 

Lecture Topics 
1 

DSP algorithms reviews: FIR and IIR filters, Fourier transform, DFT/FFT, DCT, DSP applications 



2 





3 

DSP Systems using DSP processors: TIÕs DSP processors, architecture, assembly languages, fixedpoint C programming 



4 





5 

VLSI design for DSP (1): Overview, iteration bound 



6 

VLSI design for DSP (2): Pipelining Parallel processing 



7 





8 

VLSI design for DSP (3): retiming 



9 

VLSI design for DSP (4): folding 



10 

Case study: DCT/Q Chip design for video processing (memory design, arithmetic circuit design, DCT/Q processor design) 



11 





12 




Final review 